PCB layout design for high-speed digital circuit

Client Context

A UK-based manufacturer developed a product featuring high-speed communication between a microprocessor and a flash drive via SPI. The SPI clock runs at 100 MHz. During EMC testing, significant narrowband radiated emissions failures were observed in the far field, in some cases exceeding the limit line by over 15 dB.

The design had been copied from the microprocessor manufacturer’s evaluation board, which also failed radiated emissions testing—highlighting the need for independent EMC review. The client sought professional support to resolve the issue and meet EMC compliance requirements for both CE and FCC. 

Initial radiated emission test results show narrowband emission failures

Scope of Work

• Diagnose and understand the root cause of conducted and radiated EMI

• Develop workable fixes or, if needed, initiate a timely PCB re-spin

• Document lessons learned to inform future product designs

Technical Approach

Although no full anechoic chamber was available, we applied our proven hybrid RE prediction methodology, including:

• RF current probe measurements to estimate far-field radiation

• TEM cell scans to observe consistent near-field emissions

• Antenna checks in a controlled lab environment for real-world validation

• The client’s original EMC test report was used as a reference baseline.

Troubleshooting & Mitigation

Using near-field and RF current probes, we identified the 100 MHz SPI clock line as the dominant noise source. Due to its 50% duty cycle, the clock produced strong harmonics that appeared as narrowband peaks in the radiated emission spectrum.

Surprisingly, low-speed digital lines (e.g., I²C at tens of kHz) also radiated strongly at higher frequencies—due to coupling from the clock harmonics. Ferrite cores on wires offered some suppression, but the root cause lay deeper in the PCB design.

An RF current probe is placed on the motor encoder wires; the SPI clock line harmonics can be observed on this wire

Findings

• The power distribution network (PDN) was poorly designed, with inadequate decoupling capacitor layout and selection.

• High-frequency voltage fluctuations appeared across all signal and power traces

• Even static or slow-switching I/Os showed unexpected emissions due to power integrity issues

This phenomenon occurs because high-frequency current drawn from power pins can reflect into low-speed I/Os, especially when PDN impedance is not well-controlled.

 (a) For some ICs, the high-frequency currents drawn from the power pins can be much greater than the high-frequency currents in the signals (b) significant high-frequency currents appear on low-speed I/O including outputs that never change state during normal operation; Source: Todd Hubing, https://cecas.clemson.edu/cvel/workshop/pdf/AutoEMC-Workshop-Hubing.pdf 

Key Design Actions Taken

To improve PDN integrity and reduce emissions:

• Minimized distance between IC power pins and decoupling capacitors (within 1/20 of switching wavelength)

• Matched transmission line impedance to driver current profiles

• Reduced clock slew rates in firmware to lower dv/dt

• Replaced ferrite beads with series resistors on SPI lines to improve signal integrity and impedance control

• Developed a custom on-board shielding (OBS) solution grounded to the PCB 0 V plane, targeting suppression of the 100 MHz fundamental

The revised PDN and shielding effectively suppressed both the fundamental and harmonic emissions, without introducing additional design complexity such as stripline routing (Since we aimed the new design to pass EMC without re-design, from the risk point of view, we decided not to opt for stripline but rather keep the microstripline design).

On board shielding (OBS), if implemented correctly, suppresses higher frequency noise often see in the far field

Results & Validation

Following the redesign:

• The client passed radiated emissions testing without issue

• The product was successfully launched on schedule

Conclusion

This case study highlights how unexpected EMI issues can stem from power integrity, not just high-speed signals.By addressing PDN design, signal integrity, and shielding, we achieved first-time EMC compliance in the re-spin.

Key takeaway: A robust PDN strategy is often the missing link between EMC failure and success—especially in compact, high-speed digital systems.