Early-stage EMC review of a power electronics platform

Client Context

The client is an existing customer. Following the successful resolution of EMI issues on a previous product, they approached us to support the next-generation design at a much earlier stage. The objective was to reduce technical risk, avoid late-stage EMC surprises, and make informed architectural decisions before committing to hardware.

Scope of Work

The scope of this engagement was clearly defined. The client asked us to review three different power conversion topologies, assessing each from the perspectives of:

• Form factor and system integration

• Component and manufacturing cost

• EMC performance

• Thermal behaviour

The overall goal was not to identify a single “perfect” solution, but to understand the trade-offs between the options and converge on an optimal platform architecture.

Technical Approach

This was an early-stage design review, carried out at the concept and schematic level. At this stage, simulation provides the greatest leverage, allowing architectural decisions to be evaluated before layout and mechanical constraints become fixed.

Our approach combined:

• Re-drawing and formalising the client’s schematics

• SPICE-based simulation to support quantitative analysis

• Practical EMC and power electronics design experience

Because of our deep background in power electronics, simulating and comparing the three topologies was not in itself a challenge. More importantly, the process of re-drawing the schematics allowed us to identify potential issues and risks that had not yet been highlighted by the client’s internal design team.

Key Actions

• Re-drew the complete power electronics system schematics

• Applied SPICE-based simulation techniques

• Used experience-driven EMC and power electronics judgement to interpret results and risks

 Example Focus Area: PFC Topology Selection

Due to confidentiality constraints, we cannot share full system details. However, to illustrate our methodology, we present one representative part of the review: power factor correction (PFC) topology selection.

Three candidate PFC topologies were evaluated:

• Classic boost PFC with diode bridge

• Semi-bridgeless boost PFC

• Totem-pole semi-bridgeless PFC

High-Level Feedback and Observations

• For all three topologies, we recommend keeping the switching frequency below 150 kHz to avoid the lowest conducted EMC measurement band. In practice, we would typically select ~140 kHz.

• None of the candidate designs used interleaving. At the target power level, this is a sensible choice to minimise control complexity and cost. Interleaving becomes more attractive for power levels above approximately 1.5 kW.

• The classic boost PFC with a diode bridge is generally not well suited above around 500 W, as diode bridge losses become excessive at full power and low line conditions.

• The totem-pole PFC is a strong and widely adopted topology. However, it benefits from a split DC-link capacitor to avoid DC injection into the mains and to better balance DC-link impedance for improved EMI performance.

• Overall, we preferred the semi-bridgeless boost PFC, as it offers:

  • Lower losses than the classic boost topology

  • Simpler control than the totem-pole solution

  • Better loss distribution at the target power level

  • Lower development risk, cost, and time-to-market

While this was our preferred option, we also identified opportunities for further optimisation.

One potential improvement is to reduce rectifier losses by replacing diodes with FETs operated as mains-frequency synchronous rectifiers (see below). This can be achieved using a dedicated controller that emulates diode behaviour. As an example, devices such as the NXP TEA2206T can be used to drive low-side FETs as synchronous rectifiers, significantly reducing conduction losses while maintaining simple control behaviour.

This example represents only a small fraction of the full review, which cannot be shared in detail due to confidentiality. However, it demonstrates the breadth and depth of our early-stage EMC and power electronics review capability.

By engaging at the concept and schematic stage, the client was able to:

• Make informed architectural decisions

• Reduce EMC and thermal risk early

• Avoid costly redesigns later in the development cycle